M16C80 Datasheet, PDF (267/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25^oC unless otherwise
specified)
Table 28.39 Memory expansion and microprocessor modes
(with wait, accessing external memory, multiplex bus area selected)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
Parameter
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
Standard
Measuring condition _{Min. Max.} Unit
25 ns
0
ns
(Note 1)
ns
(Note 1)
ns
25 ns
th(BCLK-CS) Chip select output hold time (BCLK standard)
0
ns
th(RD-CS) Chip select output hold time (RD standard)
(Note 1)
ns
th(WR-CS) Chip select output hold time (WR standard)
td(BCLK-RD) RD signal output delay time
(Note 1)
ns
Figure 28.1
25 ns
th(BCLK-RD) RD signal output hold time
td(BCLK-WR) WR signal output delay time
–3
ns
25 ns
th(BCLK-WR) WR signal output hold time
td(DB-WR) Data output delay time (WR standard)
0
ns
(Note 1)
ns
th(WR-DB) Data output hold time (WR standard)
(Note 1)
ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard)
25 ns
th(BCLK-ALE) ALE signal output hold time (BCLK standard)
–2
ns
td(AD-ALE) ALE signal output delay time (address standard)
(Note 1)
ns
th(ALE-AD) ALE signal output hold time (address standard)
(Note 1)
ns
tdz(RD-AD) Address output flowting start time
8
ns
th(BCLK-DB) DB signal output hold time (BCLK standard)
0
ns
Note 1: Calculated according to the BCLK frequency as follows:
th(RD – AD) =
10 ⁹
f(BCLK) X 2 ^{– 20 [ns]}
10 ⁹
th(WR – AD) = _{f(BCLK) X 2 – 20 [ns]}
th(RD – CS) =
10 ⁹
f(BCLK) X 2 ^{– 20 [ns]}
th(WR – CS) =
10 ⁹
f(BCLK) X 2
– 20
[ns]
td(DB – WR) =
10⁹X m
– 40
f(BCLK) X 2
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
10 ⁹
th(WR – DB) = _{f(BCLK) X 2} – 20 _[ns]
td(AD – ALE) =
10 ⁹
f(BCLK) X 2
– 27
[ns]
th(ALE – AD) =
10 ⁹
f(BCLK) X 2
– 20
[ns]
Rev.1.00 Aug. 02, 2005 ^{Page 256} of 329
REJ09B0187-0100