M16C80 Datasheet, PDF (50/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
7. Bus
_______ __________ __________
_____
(9) DRAM controller signals (RAS, CASL, CASH, and DW)
Bits 1, 2, and 3 of the DRAM control register (address 000416) select the DRAM space and enable the
DRAM controller. The DRAM controller signals are then output when the DRAM area is accessed. Table
7.10 shows the operation of the respective signals.
_______ __________ __________
_____
Table 7.10 Operation of RAS, CASL, CASH, and DW signals
Data bus width
RAS
L
CASL
L
CASH
L
DW
Status of external data bus
H
Read data from both even and odd addresses
L
L
L
H
Read 1 byte of data from even address
16-bit
L
H
H
H
Read 1 byte of data from odd address
L
L
L
L
Write data to both even and odd addresses
L
L
H
L
Write 1 byte of data to even address
L
H
L
L
Write 1 byte of data to odd address
L
L
Not used
H
Read 1 byte of data
8-bit
L
L
Not used
L
Write 1 byte of data
(10) Software wait
A software wait can be inserted by setting the wait control register (address 000816). Figure 7.6 shows
wait control register
You can use the external area I wait bits (where I = 0 to 3) of the wait control register to specify from “No
wait” to “3 waits” for the external memory area. When you select “No wait”, the read cycle is executed in
the BCLK1 cycle. The write cycle is executed in the BCLK2 cycle (which has 1 wait). When accessing
external memory using the multiplex bus, access has two waits regardless of whether you specify “No
wait” or “1 wait” in the appropriate external area i wait bits in the wait control register.
Software waits in the internal memory (internal RAM and internal ROM) can be set using the internal
memory wait bits of the processor mode register 1 (address 000516). Setting the internal memory wait bit
= “0” sets “No wait”. Setting the internal memory wait bit = “1” specifies a wait.
The SFR area is not affected by the setting of the internal memory wait bit and is always accessed in the
BCLK2 cycle.
Table 7.11 shows the software waits and bus cycles. Figures 7.7 and 7.8 show example bus timings
when using software waits.
Rev.1.00 Aug. 02, 2005 ^{Page 39} of 329
REJ09B0187-0100