M16C80 Datasheet, PDF (169/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
20. UARTi Special Mode Register (i = 2 to 4)
The start condition detection interrupt is generated when the fall at the SDA2 pin (P70) is detected
while the SCL2 pin (P71) is in the H state. The stop condition detection interrupt is generated when the
rise at the SDA2 pin (P70) is detected while the SCL2 pin (P71) is in the H state.
The acknowledge non-detection interrupt is generated when the H level at the SDA2 pin is detected at
the 9th rise of the transmission clock.
The acknowledge detection interrupt is generated when the L level at the SDA2 pin is detected at the
9th rise of the transmission clock. Also, DMA transfer can be started when the acknowledge is de-
tected if UART2 transmission is selected as the DMAi request factor.
Bit 2 is the bus busy flag. It is set to “1” when the start condition is detected, and reset to “0” when the
stop condition is detected.
Bit 1 is the arbitration lost detection flag control bit. Arbitration detects a conflict between data trans-
mitted at SCL2 rise and data at the SDA2 pin. This detection flag is allocated to bit 11 in UART2
transmission buffer register (address 033E16). It is set to “1” when a conflict is detected. With the
arbitration lost detection flag control bit, it can be selected to update the flag in units of bits or bytes.
When this bit is set to “1”, update is set to units of byte. If a conflict is then detected, the arbitration lost
detection flag control bit will be set to “1” at the 9th rise of the clock. When updating in units of byte,
always clear (“0” interrupt) the arbitration lost detection flag control bit after the 1st byte has been
acknowledged but before the next byte starts transmitting.
Bit 3 is the SCL2 L synchronization output enable bit. When this bit is set to “1”, the P71 data register
is set to “0” in sync with the L level at the SCL2 pin.
Bit 4 is the bus collision detection sampling clock select bit. The bus collision detection interrupt is
generated when RxDi and TxDi level do not conflict with one another. When this bit is “0”, a conflict is
detected in sync with the rise of the transfer clock. When this bit is “1”, detection is made when timer
Ai (timer A0 with UART2, timer A3 with UART3 and timer A4 with UART4) underflows. Operation is
shown in Figure 20.3.
Bit 5 is the transmission enable bit automatic clear select bit. By setting this bit to “1”, the transmission
bit is automatically reset to “0” when the bus collision detection interrupt factor bit is “1” (when a conflict
is detected).
Bit 6 is the transmission start condition select bit. By setting this bit to “1”, TxDi transmission starts in
sync with the falling at the RxDi pin.
Rev.1.00 Aug. 02, 2005 ^{Page 158} of 329
REJ09B0187-0100