M16C80 Datasheet, PDF (21/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
1. Overview
Pin Description (2)
Pin name Signal name
P40 to P47 I/O port P4
I/O type
Function
I/O This is an 8-bit I/O port equivalent to P0.
A16 to A22,
A23
CS0 to CS3
MA8 to MA12
P50 to P57 I/O port P5
O
These pins output 8 high-order address bits (A16–A22, A23). Highest
address bit (A23) outputs inversely.
O
These pins output CS0–CS3 signals. CS0–CS3 are chip select
signals used to specify an access space.
O
If accessing to DRAM area, these pins output row address and
column address separated in time by multiplexing.
I/O ^{This is an 8-bit I/O port equivalent to P0. P53 in this port outputs a}
divide-by-8 or divide-by-32 clock of XIN or a clock of the same
frequency as XCIN as selected by software.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
O
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
O
signals. WRL and WRH, and BHE and WR can be switched using
O
software control.
O
WRL, WRH, and RD selected
O
With a 16-bit external data bus, data is written to even addresses
I
when the WRL signal is “L” and to the odd addresses when the
WRH signal is “L”. Data is read when RD is “L”.
O
WR, BHE, and RD selected
I
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when
using an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs an “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the bus of microcomputer is in the wait state.
DW,
CASL,
CASH,
RAS
O
When accessing to DRAM area while DW signal is “L”, write to DRAM.
O
CASL and CASH show timing when latching to line address. When
O
CASL accesses to even address, and CASH to odd, these two pins
O
become “L”. RAS signal shows timing when latching to row address.
P60 to P67 I/O port P6
I/O ^{This is an 8-bit I/O port equivalent to P0. When set for input in single}
chip mode, microprocessor mode and memory expansion mode the
user can specify in units of four bits via software whether or not they
are tied to a pull-up resistance. Pins in this port also function as
UART0 and UART1 I/O pins as selected by software.
P70 to P77 I/O port P7
P80 to P84,
P86,
P87,
P85
I/O port P8
I/O port P85
P90 to P97 I/O port P9
P100 to P107 I/O port P10
I/O ^{This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N-channel}
open drain output). Pins in this port also function as timer A0–A3,
timer B5 or UART2 I/O pins as selected by software.
I/O P80 to P84, P86, and P87 are I/O ports with the same functions as P6.
I/O Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P86 and P87 can be set
I/O _{using software to function as the I/O pins for a sub clock generation}
I
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be canceled using
software. The pull-up cannot be set for this pin.
I/O This is an 8-bit I/O port equivalent to P6. Pins in this port also
function as UART3 and UART4 I/O pins, Timer B0–B4 input pins, D/A
converter output pins, A/D converter extended input pins, or A/D
trigger input pins as selected by software.
I/O This is an 8-bit I/O port equivalent to P6. Pins in this port also
function as A/D converter input pins. Furthermore, P104–P107 also
function as input pins for the key input interrupt function.
Rev.1.00 Aug. 02, 2005 ^{Page 10} of 329
REJ09B0187-0100