M16C80 Datasheet, PDF (168/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
20. UARTi Special Mode Register (i = 2 to 4)
P70/TXD2/SDA
P71/RXD2/SCL
P72/CLK2
Selector
Timer
I/O
UART2
IICM=1
delay
IICM=0
SDHI _ALS
Transmission register
UART2
Noize
Filter
DQ
Arbitration
T
IICM=1
IICM=0
Start condition detection
Stop condition detection
Reception register
UART2
S Bus
Q
R
busy
To DMAi
IICM=0 or IICM2=1
IICM=1 and
IICM2=0
UART2
transmission/NACK
interrupt request
IICM=0 or
IICM2=1
IICM=1 and
IICM2=0
To DMAi
UART2 reception/ACK
interrupt request
DMAi request
Noize
Filter
Noize
Filter
Falling edge
detection
L-synchronous
output enabling bit
DQ
NACK
T
I/0
Selector
UART2
IICM=1
IICM=1
R
Data register
Internal clock
DQ
T ACK
9th pulse
IICM=1
SWC2 _CLK
control
Bus collision
detection
External clock
UART2
IICM=0
Bus collision/start, stop
condition detection
interrupt request
IICM=0
UART2
IICM=0
Serector
I/0
Timer
R
Falling edge of 9th pulse
S
SWC
Port reading
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
Figure 20.2 Functional block diagram for I²C mode
Figure 20.2 is a block diagram of the IIC bus interface.
To explain the control bit of the IIC bus interface, UART2 is used as an example.
UART2 Special Mode Register (Address 033716)
Bit 0 is the IIC mode select bit. When set to “1”, ports P70, P71 and P72 operate respectively as the
SDA2 data transmission-reception pin, SCL2 clock I/O pin and port P72. A delay circuit is added to
SDA2 transmission output, therefore after SCL2 is sufficiently L level, SDA2 output changes. Port P71
(SCL2) is designed to read pin level regardless of the content of the port direction register. SDA2
transmission output is initially set to port P70 in this mode. Furthermore, interrupt factors for the bus
collision detection interrupt, UART2 transmission interrupt and UART2 reception interrupt change
respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and
acknowledge detection interrupt.
Rev.1.00 Aug. 02, 2005 ^{Page 157} of 329
REJ09B0187-0100