M16C80 Datasheet, PDF (194/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
25. DRAM Controller
25. DRAM Controller
There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of
DRAM. Table 25.1 shows the functions of the DRAM controller.
Table 25.1 DRAM Controller Functions
DRAM space
512KB, 1MB, 2MB, 4MB, 8MB
Bus control
Refresh
2CAS/1W
________
________
CAS before RAS refresh
Self refresh-compatible
Function modes
EDO-compatible, fast page mode-compatible
Waits
1 wait or 2 waits, programmable
To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 004016)
to specify the DRAM size. Figure 25.1 shows the DRAM control register.
The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 000516 are “112”).
Always use the DRAM controller in external memory modes 0, 1, or 2.
When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 000416).
Set wait time between after DRAM power ON and before memory processing, and processing necessary
for dummy cycle to refresh DRAM by software.
DRAM control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DRAMCONT
Address
0004016
When reset
Indeterminate (Note 4)
Bit symbol
WT
Bit name
Wait select bit (Note 1)
Function
0 : Two wait
1 : One wait
RW
AR0
AR1
AR2
DRAM space select bit
b3 b2 b1
0 0 0 : DRAM ignored
0 0 1 : Inhibit
0 1 0 : 0.5MB
0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
1 1 1 : Inhibit
Nothing is assigned.
When write, set "0". When read, the value of these bits is indeterminate.
SREF
Self-refresh mode bit
(Note 2)
0: Self-refresh OFF
1: Self-refresh ON
Note 1: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1.
Note 2: When you set "1", both RAS and CAS change to "L". When you set "0",
RAS and CAS change to "H" and then normal operation (read/write, refresh)
is resumed. In Stop mode, there is no control.
Note 3: Set the bus width using the external data bus width control register (address
000B16). When selecting 8-bit bus width, CASH is indeterminate.
Note 4: After reset, the content of this register is indeterminate.
DRAM controller starts the operation after writing to this register.
Figure 25.1 DRAM control register
Rev.1.00 Aug. 02, 2005 ^{Page 183} of 329
REJ09B0187-0100