M16C80 Datasheet, PDF (80/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
9.15 Return from Interrupt Routine
As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register
(FLG) and program counter (PC) that have been saved to the stack area immediately preceding the
interrupt sequence are automatically restored. In high-speed interrupt, as you execute the FREIT instruc-
tion at the end of the interrupt routine, the contents of the flag register (FLG) and program counter (PC)
that have been saved to the save registers immediately preceding the interrupt sequence are automati-
cally restored.
Then control returns to the routine that was under execution before the interrupt request was acknowl-
edged, and processing is resumed from where control left off.
If there are any registers you saved via software in the interrupt routine, be sure to restore them using an
instruction (e.g., POPM instruction) before executing the REIT or FREIT instruction.
When switching the register bank before executing REIT and FREIT instruction, switched to the register
bank immediately before the interrupt sequence.
9.16 Interrupt Priority
If two or more interrupt requests are sampled active at the same time, whichever interrupt request is
acknowledged that has the highest priority.
Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the inter-
rupt priority level select bit accordingly. If some maskable interrupts are assigned the same priority level,
the priority between these interrupts is resolved by the priority that is set in hardware.
Certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer
interrupt have their priority levels set in hardware. Figure 9.7 lists the hardware priority levels of these
interrupts.
Software interrupts are not subjected to interrupt priority. They always cause control to branch to an
interrupt routine whenever the relevant instruction is executed.
9.17 Interrupt Resolution Circuit
Interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are
sampled active at the same time.
Figure 9.8 shows the interrupt resolution circuit.
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Reset > NMI > Watchdog > Peripheral I/O > Single step > Address match
Figure 9.7 Interrupt priority that is set in hardware
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