M16C80 Datasheet, PDF (135/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
16. Serial I/O
16. Serial I/O
Serial I/O is configured as five channels: UART0 to UART4.
UART0 to 4
UART0 to UART4 each have an exclusive timer to generate a transfer clock, so they operate independently
of each other.
Figures 16.1 and 16.2 show the block diagram of UARTi (i=0 to 4). Figures 16.3 and 16.4 show the block
diagram of the transmit/receive unit.
UARTi has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O
mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 036016,
036816, 033816, 032816 and 02F816) determine whether UARTi is used as a clock synchronous serial I/O or
as a UART.
Although a few functions are different, UART0 to UART4 have almost the same functions.
UART2 to UART4, in particular, are compliant with the SIM interface with some extra settings added in
clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates
an interrupt request if the TxD pin and the RxD pin are different in level.
Table 16.1 shows the comparison of functions of UART0 to UART4, and Figures 16.5 through 16.11 show
the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table 16.1 Comparison of functions of UART0 to UART4
Function
UART0
UART1
UART2
CLK polarity selection
Possible^{(Note 1)} Possible^{(Note 1)} Possible^{(Note 1)}
UART3
UART4
Possible^{(Note 1)} Possible^{(Note 1)}
LSB first / MSB first selection Possible ^{(Note 1)} Possible^{(Note 1)} Possible^{(Note 2)} Possible^{(Note 2)} Possible^{(Note 2)}
Continuous receive mode
selection
Transfer clock output from
multiple pins selection
Separate CTS/RTS pins
Possible ^{(Note 1)} Possible^{(Note 1)} Possible^{(Note 1)} Possible^{(Note 1)} Possible^{(Note 1)}
Impossible
Possible^{(Note 1)} Impossible
Impossible
Impossible
Possible
Impossible
Impossible
Impossible
Impossible
Serial data logic switch
Impossible
Impossible
Possible^{(Note 4)} Possible^{(Note 4)} Possible^{(Note 4)}
Sleep mode selection
Possible^{(Note 3)} Possible ^{(Note 3)} Impossible
Impossible
Impossible
TxD, RxD I/O polarity switch Impossible
Impossible
Possible
Possible
Possible
TxD, RxD port output format CMOS output
Parity error signal output
Impossible
CMOS output
Impossible
N-channel open
drain output
CMOS output
CMOS output
Possible^{(Note 4)} Possible^{(Note 4)} Possible^{(Note 4)}
Bus collision detection
Impossible
Impossible
Possible
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
Possible
Possible
Rev.1.00 Aug. 02, 2005 ^{Page 124} of 329
REJ09B0187-0100