M16C80 Datasheet, PDF (73/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
9.6 Interrupt control registers
Peripheral I/O interrupts have their own interrupt control registers. Figure 9.3 shows the interrupt control
registers.
When using an interrupt to exit Stop mode or Wait mode, the relevant interrupt must have been enabled
and set to a priority level above the level set by the interrupt priority set bits for exit a stop/wait state (bits
2, 1, and 0 at address 009F16). Set the interrupt priority set bits for the exit from a stop/wait state to the
same level as the flag register (FLG) processor interrupt level (IPL).
Figure 9.4 shows the exit priority register.
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REJ09B0187-0100