M16C80 Datasheet, PDF (55/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
8. Clock Generating Circuit
8.2 Clock Control
Figure 8.3 shows the block diagram of the clock generating circuit.
XCIN
CM04
XCOUT
CM10 “1”
Write signal
RESET
Software reset
NMI
Interrupt request
level judgment
output
WAIT instruction
SQ
R
SQ
R
Sub clock
XIN
XOUT
Main clock
CM05
CM02
1/32 ^fC32
f1
fC
fAD
f8
f32
bc
a _{Divider 1}
f1SIO2
f8SIO2
f32SIO2
d _{Divider 2} e ^CM07=0
fC
CM07=1
BCLK
b
c
a
1/2
1/2
1/2
1/2
1/2
Details of divider 1
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
a
1/N divider
N is set by MCD4 to MCD0 as follow:
N = 1, 2, 3, 4, 6, 8, 10, 12, 14 and 16
Figure 8.3 Clock generating circuit
e
Details of divider 2
Rev.1.00 Aug. 02, 2005 ^{Page 44} of 329
REJ09B0187-0100