M16C80 Datasheet, PDF (198/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
25. DRAM Controller
< Read cycle (wait control bit = 0) >
BCLK
MA0 to MA12
Row
address
RAS
CASH
CASL
'H'
DW
Column
address 1
D0 to D15
(EDO mode)
Note : Only CASL is operating in 8-bit data bus width.
Column
address 2
< Write cycle (wait control bit = 0) >
BCLK
MA0 to MA12
Row
address
Column
address 1
RAS
CASH
CASL
DW
D0 to D15
Note : Only CASL is operating in 8-bit data bus width.
Column
address 2
Column
address 3
Column
address 3
Figure 25.4 The bus timing during DRAM access (1)
Rev.1.00 Aug. 02, 2005 ^{Page 187} of 329
REJ09B0187-0100