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M16C80 Datasheet, PDF (27/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES | |||
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M16C/80 Group
3. Central Processing Unit (CPU)
(17) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 3.2 shows the flag
register (FLG). The following explains the function of each flag:
⢠Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
⢠Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is â1â, a single-step interrupt is generated after instruction execution. This flag is
cleared to â0â when the interrupt is acknowledged.
⢠Bit 2: Zero flag (Z flag)
This flag is set to â1â when an arithmetic operation resulted in 0; otherwise, cleared to â0â.
⢠Bit 3: Sign flag (S flag)
This flag is set to â1â when an arithmetic operation resulted in a negative value; otherwise, cleared
to â0â.
⢠Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is â0â ; register bank
1 is selected when this flag is â1â.
⢠Bit 5: Overflow flag (O flag)
This flag is set to â1â when an arithmetic operation resulted in overflow; otherwise, cleared to â0â.
⢠Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is â0â, and is enabled when this flag is â1â. This flag is
cleared to â0â when the interrupt is acknowledged.
⢠Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is â0â ; user stack pointer (USP) is selected
when this flag is â1â.
This flag is cleared to â0â when a hardware interrupt is acknowledged or an INT instruction of
software interrupt Nos. 0 to 31 is executed.
⢠Bits 8 to 11: Reserved area
Rev.1.00 Aug. 02, 2005 Page 16 of 329
REJ09B0187-0100
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