M16C80 Datasheet, PDF (246/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25^oC unless otherwise
specified)
Table 28.22 Memory expansion mode and microprocessor mode
(with wait, accessing external memory, DRAM area selected)
Symbol
Parameter
Measuring condition
Standard
Min. Max.
Unit
td(BCLK-RAD) ^{Row address output delay time}
18 ns
th(BCLK-RAD) Row address output hold time (BCLK standard)
td(BCLK-CAD) ^{String address output delay time}
-3
ns
18 ^ns
th(BCLK-CAD) String address output hold time (BCLK standard)
-3
ns
th(RAS-RAD) ^{Row address output hold time after RAS output}
(Note 1)
ns
td(BCLK-RAS) RAS output delay time (BCLK standard)
Figure 28.1
18 ns
th(BCLK-RAS) RAS output hold time (BCLK standard)
-3
ns
tRP
RAS "H" hold time
(Note 1)
ns
td(BCLK-CAS) CAS output delay time (BCLK standard)
18 _ns
th(BCLK-CAS) ^{CAS output hold time (BCLK standard)}
td(BCLK-DW) ^{Data output delay time (BCLK standard)}
-3
ns
18 ns
th(BCLK-DW) ^{Data output hold time (BCLK standard)}
tsu(DB-CAS) ^{CAS after DB output setup time}
-5
ns
(Note 1)
ns
th(BCLK-DB) DB signal output hold time (BCLK standard)
-7
ns
tsu(CAS-RAS) ^{CAS before RAS setup time (refresh)}
(Note 1)
ns
Note 1: Calculated according to the BCLK frequency as follows:
th(RAS – RAD) =
10 ⁹
f(BCLK) X 2 ^{– 13} [ns]
tRP =
tsu(DB – CAS) =
tsu(CAS – RAS) =
10 ⁹ X 3
– 20
f(BCLK) X 2
[ns]
10 ⁹
– 20
f(BCLK)
[ns]
10⁹
f(BCLK) X 2 ^{– 13} [ns]
Rev.1.00 Aug. 02, 2005 ^{Page 235} of 329
REJ09B0187-0100