M16C80 Datasheet, PDF (163/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)
Tc
Transfer Clock
Transmit rnable ^"1"
bit (TE)
"0"
Transmit enable "1"
empty flag (TI)
"0"
TxDi
RxDi
Signal conductor level
(Note 2)
Transmit register _"1"
empty flag
(TXEPT)
"0"
Transmit interrupt "1"
request bit (IR)
"0"
Data is set in the UARTi
transmit buffer register
(Note 1)
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
The level is detected by
the interrupt routine
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Transferred from the UARTi transmit buffer
register to the UARTi transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An "L" level returns from SIM card
due to the occurrence of a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
The level is detected by
the interrupt routine
Shown in () are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit
• Transmit interrupt cause select bit = "1".
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / fEXT
fi : frequency of BRGi rcount source (f1, f8, f32)
fEXT : frequency of BRGi rcount source (external clock)
n : value set to BRGi
Tc
Transfer Clock
Receive enable bit
(RE)
"1
"
"0
"
RxDi
TxDi
Signal conductor level
(Note 2)
Transmit register
empty flag
"1"
(TXEPT)
"0
"
Transmit interrupt "1"
request bit (IR)
"0"
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An "L" level returns from TxDi due to
the occurrence of a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
Read to receive buffer
Read to receive buffer
Shown in () are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit
• Transmit interrupt cause select bit = "0".
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / fEXT
fi : frequency of BRGi rcount source (f1, f8, f32)
fEXT : frequency of BRGi rcount source (external clock)
n : value set to BRGi
Note 1: After writing to the transfer buffer at above timing, transmission starts at the timing of BRG overflow.
Note 2: Equal in waveform because TxDi and RxDi are connected.
Figure 19.1 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Rev.1.00 Aug. 02, 2005 ^{Page 152} of 329
REJ09B0187-0100