M16C80 Datasheet, PDF (46/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
7. Bus
(3) Read/write signals
With a 16-bit data bus, bit 2 of the processor mode register 0 (address 000416) select the combinations of
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RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the
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combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode
register 0 (address 000416).) When using both 8-bit and 16-bit data bus widths and you access an 8-bit
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data bus area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the
processor mode register 0 (address 000416).
Tables 7.5 and 7.6 show the operation of these signals.
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After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
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When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
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Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals.
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Table 7.5 Operation of RD, WRL, and WRH signals
Data bus width
RD
WRL
WRH
L
H
H
16-bit
H
L
H
H
H
L
H
L
L
8-bit
H
L
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Note: It becomes WR signal.
L (Note) Not used
H (Note) Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
Write 1 byte of data
Read 1 byte of data
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Table 7.6 Operation of RD, WR, and BHE signals
Data bus width
RD
WR
BHE
A0
H
L
L
H
L
H
L
H
16-bit
H
L
H
L
L
H
H
L
H
L
L
L
L
H
L
L
H
L
Not used
H/L
8-bit
L
H
Not used
H/L
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
Rev.1.00 Aug. 02, 2005 ^{Page 35} of 329
REJ09B0187-0100