M16C80 Datasheet, PDF (275/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 1 wait)
Read Timing
BCLK
tcyc
td(BCLK-RAD) ^th(BCLK-RAD)
25ns.max*1 0ns.min
td(BCLK-CAD)
25ns.max*1
th(BCLK-CAD)
0ns.min
MAi
Row address
String address
th(RAS-RAD)*2
tRP*2
RAS
CASL
CASH
DW
DB
td(BCLK-RAS)
25ns.max*1
th(BCLK-RAS)
td(BCLK-CAS)
0ns.min
25ns.max*1
th(BCLK-CAS)
0ns.min
tac4(CAS-DB)*2
tac4(CAD-DB)*2
tac4(RAS-DB)*2
Hi-Z
tsu(DB-BCLK)
40ns.min*1
th(CAS-DB)
0ns.min
Vcc=3V
*1:It is a guarantee value with being alone. 55ns.max garantees as follows:
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
*2:It depends on operation frequency.
tac4(RAS-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
tac4(CAS-DB)=(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
tac4(CAD-DB)=(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
th(RAS-RAD)=(tcyc/2-25)ns.min
tRP=(tcyc/2 x 3-40)ns.min
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Figure 28.21 VCC=3V timing diagram (7)
Rev.1.00 Aug. 02, 2005 ^{Page 264} of 329
REJ09B0187-0100