M16C80 Datasheet, PDF (351/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
Revision History
Version
Contents for change
Page 217 Setting the registers, Notes on the microprocessor mode ... single-chip mode
-
->addition
Page 217 Explanation of note on Flash memroy version is added.
Page 219 Note 2 80mA --> –80mA
Page 220 Table 1.28.3 Ta --> Topr, Note2 --> addition
Pages 220, 243 Tables 1.28.3, 1.28.23 Icc Power supply current ROMless version --> addi-
tion, Ta --> Topr, Note 2 --> addition
Page 227 Calculation for td(AD-ALE) is partly revised.
Page 234, 235 Figures 1.28.6 and 1.28.7 Timing for td(AD-ALE) is partly revised.
Page 243 Table 1.28.23 Topr=25°C, when clock is stopped: 2.0µA --> 1.0µA, Notes 1, 2 -->
addition
Page 250 Table 1.28.41 th(BCLK-RD) Min. 0 ns --> –3 ns
Pages 251, 258 to 262 Table 1.28.42, figures 1.28.21 to 1.28.25 th(BCLK-CAS): –3 ns -->
0 ns
Pages 251, 259, 261 Table 1.28,42, figures 1.28.22, 1.28.24 th(BCLK-DW): 0 ns --> –3 ns
Page 266 Table 1.29.2 M30805FGGP RAM capacity 24 Kbytes --> 20 Kbytes
Page 270 Figure 1.30.1 Flash memory control register 0 Note 1 Also write to this bit ... "H"
level. --> addition
Page 273 (3) Disabling erase or ... serial I/O mode --> delete, (7), (8) --> addition
Page 285 Note --> addition
Page 288 --> addition
Pages 291, 307 Tables 1.31.1, 1.31.5 Note 2 ... status register 1 data --> ... status register
data 1
Page 319 144P6Q-A version --> addition
Rev.E1 _{Page 32 Table 1.7.3 --> change}
Revision
date
16/03/'01
Rev.E2 Page 28 Figure 1.6.1 Note 8 --> addition
Page 88 Table for "Coefficient j, k" is partly revised.
Rev.E3
Page 7 Figure 1.1.5 and Table 1.1.2, product names --> added
Page 8 Figure 1.1.6, Boot loader (BL) -->addition
Page 85 Figure 1.11.5, DMAi SFR address register, Note 2, destination fixed address -->
source fixed address, source fixed address --> destination fixed address
Page 218 Precaution of boot loader --> addition
Page 319 Appendix boot loader --> addition
Rev.1.0 Page 4 Figure 1.3 XOUT --> revised
Page 18 Figure 4.1 and 4.2 --> revised
Page 20 Figure 4.3, Timer B3 mode register value 00?x0000 --> 00??0000
Three-phase output buffer register 0, 1 value 0016 --> 3F16
Page 21 Figure 4.4, Timer B0 mode register value 00?x0000 --> 00??0000
UART transmit/receive control register 2 value x0000000 --> x0xx0000
Flash memory control register1 value ?????0?? --> ????0???
Page 22 (address006A16) DM1IC --> DM2IC revised
Page 24 (address037016) UCON2 --> UCON revised
Page 26 "Carry out a software reset after oscillation of main clock is fully stable"--> added,
(1), (2) --> revised
Page 27 Figure 6.1 10:Inhibited --> 10:Must not be set
10/05/'01
20/08/'01
02/08/'05
C- 11