M16C80 Datasheet, PDF (346/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
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Page 25 Figure 1.6.1, 1.6.2 Figure 1.6.1 is divided to Figure 1.6.1and 1.6.2
Page 30 Table 1.7.4
Page 34 Figure 1.7.3
Note addition
Page 36 Line 3 the chip select control register --> the wait control registe
Page 38, 39 Figure 1.7.6, 1.7.7 Note change
Page 42 Line 7 addition
When the main clock is stoped (bit 5 at address 000616 =1) or the mode is shifted to
stop mode (bit 0 at address 000716 =1), the main clock division register (address
000C16) is set to the divided-8 mode.
Page 42 (3)BCLK When shifting to stop mode, --> When main clock is stoped or shifting to
stop mode,
Page 43 Figure 1.8.4
CM0 Note 6 change, Note 7, 8 addition, CM1 Note 4 addition
Page 44 Figure 1.8.5
Note 2 change
Page 48 Line 5 When shifting to stop mode and reset, --> When shifting to stop mode,
reset or stopping main clock,
(12) Low power dissipation mode addition
When the main clock is stoped, the main clock division register (address 000C16) is
set to the division by 8 mode.
Page 51 Figure 1.8.7. Clock transition Note 3, 4 addition
Page 52 Line 9 addition
Page 54 Software Interrupts (2) Overflow interrupt, "CMPX" addition
Page 55 (2) Peripheral I/O interrupts
• Bus collision detection/start, stop condition (UART2, UART3, UART4) interrupts -->
change
Page 57 • Variable vector tables addition
Set an even address to the start address of vector table setting in INTB so that
operating efficiency is increased.
Page 58 Table 1.9.3
Bus collision detection/start, stop condition interrupts --> Bus collision detection, start/
stop condition detection interrupts
Page 58 Table 1.9.3, page 68 Figure 1.9.8
Software interrupt number 40, 41 fault errir --> addition
Page 71 Address match interrupt Line 7 addition
_______
Page 72 (3) The NMI interrupt
_______
• Do not reset the CPU with the input to the NMI pin being in the “L” state. --> • Signal
of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for
_______
NMI pin.
Page 72 (4) External interrupt
Page 74 Figure 1.10.1
Page 76 Line 2
"DMAC is a function that to transmit 1 data of a source address (8 bits /16 bits) to a
destination address when transmission request occurs. " addition.
Page 76 Line 12 addition
When writing to DSA2 and DSA3, set register bank select flag (B flag) to "1" and use
LDC instruction to set SB and FB registers.
Page 76 Figure 1.11.1
Page 77 Table 1.11.1
Transfer memory space (16 Mbyte space) --> addition
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