M16C80 Datasheet, PDF (97/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
11. DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of external data bus width control register
When in memory expansion mode or microprocessor mode, the transfer cycle changes according to
the data bus width at the source and destination.
1. When transferring 16 bits of data and the data bus width at the source and at the destination is 8
bits (data bus width bit = “0”), there are two 8-bit data transfers. Therefore, two bus cycles are
required for reading and two cycles for writing.
2. When transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit
= “0”) and the data bus width at the destination is 16 bits (data bus width bit = “1”), the data is read
in two 8-bit blocks and written as 16-bit data. Therefore, two bus cycles are required for reading
and one cycle for writing.
3. When transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit
= “1”) and the data bus width at the destination is 8 bits (data bus width bit = “0”), 16 bits of data are
read and written as two 8-bit blocks. Therefore, one bus cycle is required for reading and two
cycles for writing.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 11.6 shows the example of the transfer cycles for a source read. Figure 11.6 shows the destination
is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source read
cycles for the different conditions. In reality, the destination write cycle is subject to the same conditions
as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer
cycle, remember to apply the respective conditions to both the destination write cycle and the source read
cycle. For example (2) in Figure 11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus
cycles are required for both the source read cycle and the destination write cycle.
Rev.1.00 Aug. 02, 2005 ^{Page 86} of 329
REJ09B0187-0100