English
Language : 

M16C80 Datasheet, PDF (83/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES
M16C/80 Group
9. Interrupt Outline
______
9.19 NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03C416).
This pin cannot be used as a normal port input.
Notes:
______
______
______
When not intending to use the NMI function, be sure to connect the NMI pin to VCC (pulled-up). The NMI
interrupt is non-maskable. Because it cannot be disabled, the pin must be pulled up.
9.20 Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A/D input ports. Figure 9.10 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Setting the key input interrupt disable bit (bit 7 at address 03AF16) to “1” disables key input interrupts from
occurring regardless of the setting in the interrupt control register. When “1” is set in the key input interrupt
disable register, there is no input via the port pin even when the direction register is set to input.
Pull-up
transistor
Port P104-P107 pull-up
select bit
Port P107 direction
register
key input interrupt
disable bit
Port P107 direction register
P107/KI3
Pull-up
transistor
P106/KI2
Port P106 direction
register
Pull-up
transistor
P105/KI1
Pull-up
transistor
P104/KI0
Port P105 direction
register
Port P104 direction
register
Key input interrupt control
register
(address 009316)
Interrupt control
circuit
Key input interrupt
request
Figure 9.10 Block diagram of key input interrupt
Rev.1.00 Aug. 02, 2005 Page 72 of 329
REJ09B0187-0100