M16C80 Datasheet, PDF (39/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
6. Processor Mode
Processor mode register 1 (Note 1) :Mask ROM version
ROMless version (144-pin version)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM1
Address
000516
When reset
0016
Bit symbol
PM10
Bit name
External memory area
mode bit (Note 3)
PM11
PM12
Internal memory wait bit
Function
RW
b1 b0
0 0 : Mode 0 (P44 to P47 : A20 to A23)
0 1 : Mode 1 (P44 : A20,
P45 to P47 : CS2 to CS0)
1 0 : Mode 2 (P44, P45 : A20, A21,
P46, P47 : CS1, CS0)
1 1 : Mode 3 (Note 2)
(P44 to P47 : CS3 to CS0)
0 : No wait state
1 : Wait state inserted
Reserved bit
Must always be set to “0”
PM14
PM15
ALE pin select bit (Note 3)
b5 b4
0 0 : No ALE
0 1 : P53/BCLK (Note 4)
1 0 : P56/RAS
1 1 : P54/HLDA
Nothing is assinged. When read, the content is indeterminate.
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Processor mode register 1 (Note 1) :Flash memory version
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM1
Address
000516
When reset
0016
Bit symbol
PM10
PM11
PM12
Bit name
External memory area
mode bit (Note 3)
Internal memory wait bit
Function
b1 b0
0 0 : Mode 0 (P44 to P47 : A20 to A23)
0 1 : Mode 1 (P44 : A20,
P45 to P47 : CS2 to CS0)
1 0 : Mode 2 (P44, P45 : A20, A21,
P46, P47 : CS1, CS0)
1 1 : Mode 3 (Note 2)
(P44 to P47 : CS3 to CS0)
0 : No wait state
1 : Wait state inserted
RW
Reserved bit
Must always be set to “0”
PM14
PM15
ALE pin select bit (Note 3)
b5 b4
0 0 : No ALE
0 1 : P53/BCLK (Note 4)
1 0 : P56/RAS
1 1 : P54/HLDA
Reserved bit
Must always be set to “1” (Note 5)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Note 5: Rewrite this bit when the main clock is in division by 8 mode.
Figure 6.2 Processor mode register 1
Rev.1.00 Aug. 02, 2005 ^{Page 28} of 329
REJ09B0187-0100