M16C80 Datasheet, PDF (228/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
27. Usage Precaution
Interrupt C routine
Interrupt_C:
pushm R0,R1,R2,R3,A0,A1
fset I
••••
••••
popm R0,R1,R2,R3,A0,A1
fclr U
pushm R0
mov.w 6[SP],R0
ldc R0,FLG
popm R0
nop
reit
; Store registers
; Multiple interrupt enabled
;Restore registers
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
; Read FLG on stack
; Set in FLG
; Restore R0 register
; Dummy
; Interrupt completed
(4) External interrupt
• Edge sense
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
to INT5 regardless of the CPU operation clock.
• Level sense
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division
mode, at least 250 ns width is necessary.)
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 27.2 shows the procedure for
______
changing the INT interrupt generate factor.
Set the interrupt priority level to level 0
(Disable INT interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INT interrupt request)
______
Figure 27.2 Switching condition of INT interrupt request
Rev.1.00 Aug. 02, 2005 ^{Page 217} of 329
REJ09B0187-0100