M16C80 Datasheet, PDF (84/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
9.21 Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Four address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 9.11 shows the address match interrupt-related registers.
Set the start address of an instruction to the address match interrupt register.
Address match interrupt is not generated when address such as the middle of instruction or table data is
set.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXX00002
Bit symbol
AIER0
Bit name
Address match interrupt 0
enable bit
AIER1 ^{Address match interrupt 1}
enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
AIER2 ^{Address match interrupt 2} 0 : Interrupt disabled
enable bit _{1 : Interrupt enabled}
AIER3 ^{Address match interrupt 3} 0 : Interrupt disabled
enable bit 1 : Interrupt enabled
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
RW
Address match interrupt register i (i = 0 ot 3)
(b23)
b7
(b16)(b15)
b0 b7
(b8)
b0 b7
Symbol
b0 ^RMAD0
RMAD1
RMAD2
RMAD3
Function
Address setting register for address match
interrupt
Address
001216 to 001016
001616 to 001416
001A16 to 001816
001E16 to 001C16
When reset
00000016
00000016
00000016
00000016
Values that can be set R W
00000016 to FFFFFF16
Figure 9.11 Address match interrupt-related registers
Rev.1.00 Aug. 02, 2005 ^{Page 73} of 329
REJ09B0187-0100