M16C80 Datasheet, PDF (273/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
Memory expansion Mode and Microprocessor Mode
(When accessing external memory area with 2 wait, and select multiplexed bus)
Read Timing
Vcc=3V
BCLK
ALE
CSi
ADi
/DBi
ADi
BHE
RD
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
tcyc
25ns.max
td(AD-ALE)*1 th(ALE-AD)*1
Address
td(BCLK-AD)
25ns.max
tdz(RD-AD)
8ns.max
tac3(RD-DB)*1
th(RD-CS)*1
th(BCLK-CS)
0ns.min
Data input
tsu(DB-BCLK)
40ns.min
Address
th(RD-DB)
0ns.min _th(BCLK-AD)
0ns.min
tac3(AD-DB)*1
td(BCLK-RD)
25ns.max
th(BCLK-RD)
-3ns.min
th(RD-AD)*1
*1:It depends on operation frequency.
td(AD-ALE)=(tcyc/2-27)ns.min
th(ALE-AD)=(tcyc/2-20)ns.min, th(RD-AD)=(tcyc/2-20)ns.min, th(RD-CS)=(tcyc/2-20)ns.min
tac3(RD-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
tac3(AD-DB)=(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
Write Timing
BCLK
ALE
td(BCLK-ALE) _th(BCLK-ALE)
25ns.max
-2ns.min
CSi
ADi
/DBi
td(BCLK-CS)
tcyc
25ns.max
td(AD-ALE)*2 _th(ALE-AD)*2
Address
ADi
BHE
td(BCLK-AD)
25ns.max
WR,WRL,
WRH
td(BCLK-WR)
25ns.max
th(WR-CS)*2
th(BCLK-CS)
0ns.min
Data output
td(DB-WR)*2
th(BCLK-DB)
0ns.min
Address
th(WR-DB)*2
th(BCLK-AD)
0ns.min
th(BCLK-WR)
0ns.min
th(WR-AD)*2
*2:It depends on operation frequency.
td(AD-ALE)=(tcyc/2-27)ns.min
th(ALE-AD)=(tcyc/2-20)ns.min, th(WR-AD)=(tcyc/2-20)ns.min
th(WR-CS)=(tcyc/2-20)ns.min, th(WR-DB)=(tcyc/2-20)ns.min
td(DB-WR)=(tcyc/2 x m-40)ns.min
(m=3 and 5 when 2 wait and 3 wait, respectively.)
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Figure 28.19 VCC=3V timing diagram (5)
Rev.1.00 Aug. 02, 2005 ^{Page 262} of 329
REJ09B0187-0100