M16C80 Datasheet, PDF (45/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
7. Bus
The chip select signal turns “L” (active) in synchronize with the address bus. However, its turning “H”
depends on the area accessed in the next cycle. Figure 7.2 shows the output examples of the address
bus and chip select signals.
(Example 1) After accessing the external area, the address bus and chip
select signal both are changed in the next cycle.
The following example shows the other chip select signal accessing
area (j) in the cycle after having accessed external area (i). In this
case, the address bus and chip select signal both change between the
two cycles.
Access to Access to
external external
area (i) area (j)
(Example 2) After accessing the external area, only the chip select signal
is changed in the next cycle. (The address bus does not
change.)
The following example shows the CPU accesses the internal
ROM/RAM area in the cycle after having accessed external
area. In this case, the chip select signal changes between the
two cycles but the address bus does not.
Data bus
Address bus
Chip select
(CSi)
Chip select
(CSj)
Data
Data
Address
Data bus
Address bus
Chip select
Data
Address
(Example 3) After accessing the external area, only the address bus is
changed in the next cycle. (The chip select signal does not
change.)
The following example shows the same chip select signal
accessing area (i) in the cycle after having accessed
external area (i). In this case, the address bus changes
between the two cycles, but the chip select signal does not.
(Example 4) After accessing the external area, the address bus and chip
select signal both are not changed in the next cycle.
The following example shows CPU does not access any
area in the cycle after having accessed external area (no
instruction pre-fetch is occurred). In this case, the address
bus and the chip select signal do not change between the
two cycles.
Data bus
Address bus
Chip select
(CSi)
Access to Access to
external external
area (i) area (i)
Data
Data
Address
Data bus
Address bus
Chip select
Access to
external
area
No access
Data
Address
Note: These examples show the address bus and chip select signal for two consecutive cycles.
By combining these examples, chip select signal can be extended beyond two cycles.
Figure 7.2 Example of address bus and chip select signal outputs (Separate bus)
Rev.1.00 Aug. 02, 2005 ^{Page 34} of 329
REJ09B0187-0100