M16C80 Datasheet, PDF (254/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
Vcc=5V
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 1 wait)
Read Timing
BCLK
tcyc
td(BCLK-RAD) th(BCLK-RAD)
18ns.max _-3ns.min
MAi
Row address
td(BCLK-CAD)
18ns.max*1
th(BCLK-CAD)
-3ns.min
String address
th(RAS-RAD)*2
tRP*2
RAS
CASL
CASH
td(BCLK-RAS)
18ns.max*1
td(BCLK-CAS)
18ns.max*1
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
DW
tac4(CAS-DB)*2
tac4(CAD-DB)*2
tac4(RAS-DB)*2
DB
Hi-Z
tsu(DB-BCLK)
26ns.min*1
th(CAS-DB)
0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as follows:
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
*2:It depends on operation frequency.
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
Figure 28.8 VCC=5V timing diagram (7)
Rev.1.00 Aug. 02, 2005 ^{Page 243} of 329
REJ09B0187-0100