M16C80 Datasheet, PDF (38/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
6. Processor Mode
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM0
Address
000416
When reset
8016 (Note 2)
Bit symbol
PM00
PM01
Bit name
Processor mode bit
(Note 8)
Function
b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
RW
PM02
PM03
PM04
PM05
R/W mode select bit
(Note 7)
Software reset bit
Multiplexed bus space
select bit (Note 3)
0 : RD,BHE,WR
1 : RD,WRH,WRL
The device is reset when this bit is set to “1”.
The value of this bit is “0” when read.
b5 b4
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
Reserved bit
PM07
BCLK output disable bit
(Note 5)
Must always be set to “0”
0 : BCLK is output (Note 6)
1 : Function set by bit 0,1 of system
clock control register 0
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 is set
to “1” and PM07 is set to “0”.)
Note 3: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus when
mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.
Note 4: After the reset has been released, the M16C/80 group MCU operates using the separate bus. As a
result, in microprocessor mode, you cannot select the full CS space multiplex bus.
When you select the full CS space multiplex bus in memory expansion mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Mode 0: Multiplexed bus cannot be used.
Mode 1: CS0 to CS2 when you select full CS space.
Mode 2: CS0 to CS1 when you select full CS space.
Mode 3: CS0 to CS3 when you select full CS space.
Note 5: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock output in
microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0 (CM00) and
bit 1 (CM01) of system clock control register 0 (address 000616) = "0". "L" is now output from P53.
Note 6: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Note 7: When using 16-bit bus width in DRAM controller, set this bit to "1".
Note 8: Do not set the processor mode bits and other bits simultaneously when setting the processor mode
bits to “012” or “112”. Set the other bits first, and then change the processor mode bits.
Figure 6.1 Processor mode register 0
Rev.1.00 Aug. 02, 2005 ^{Page 27} of 329
REJ09B0187-0100