M16C80 Datasheet, PDF (52/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
7. Bus
< Separate bus (no wait) >
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Address bus (Note 2)
Chip select (Note 2,3)
< Separate bus (with wait) >
BCLK
Write signal
Read signal
Data bus
Address bus (Note 2)
Chip select (Note 2,3)
Output
Address
Bus cycle (Note)
Output
Address
Input
Address
Bus cycle (Note)
Input
Address
< Separate bus with 2 wait >
Bus cycle (Note 1)
Bus cycle (Note 1)
BCLK
Write signal
Read signal
Data bus
Address bus (Note 2)
Data output
Address
Input
Address
Chip select (Note 2,3)
Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this
bus cycle.
Note 2: Address bus and chip select may get longer by a state of CPU such as an instruction queue buffer.
Note 3: When accessing same external area (same CS area) continuously, chip select may output
continuously.
Figure 7.7 Typical bus timings using software wait
Rev.1.00 Aug. 02, 2005 ^{Page 41} of 329
REJ09B0187-0100