M16C80 Datasheet, PDF (63/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
8. Clock Generating Circuit
Note: When count source of BCLK is changed from clock A to clock B (XIN to XCIN or XCIN to XIN), clock B
needs to be stable before changing. Please wait to change modes until after oscillation has stabilized.
Table 8.6 Operating modes dictated by settings of system clock control register 0 and main clock division register
CM07 CM05 CM04 MCD4 MCD3 MCD2 MCD1 MCD0 Operating mode of BCLK
0
0 Invalid 1
0
0
1
0 No division
0
0 Invalid 0
0
0
1
0 Division by 2 mode
0
0 Invalid 0
0
0
1
1 Division by 3 mode
0
0 Invalid 0
0
1
0
0 Division by 4 mode
0
0 Invalid 0
0
1
1
0 Division by 6 mode
0
0 Invalid 0
1
0
0
0 Division by 8 mode
0
0 Invalid 0
1
0
1
0 Division by 10 mode
0
0 Invalid 0
1
1
0
0 Division by 12 mode
0
0 Invalid 0
1
1
1
0 Division by 14 mode
0
0 Invalid 0
0
0
0
0 Division by 16 mode
1
0
1 Invalid Invalid Invalid Invalid Invalid Low-speed mode
1
1
1 Invalid Invalid Invalid Invalid Invalid Low power dissipation mode
CM0i: Clock control register 0 (address 000616) bit i
MCDi: Main clock division register (address 000C16) bit i
Rev.1.00 Aug. 02, 2005 ^{Page 52} of 329
REJ09B0187-0100