M16C80 Datasheet, PDF (299/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
30. CPU Rewrite Mode
Functions To Prevent the Flash Memory from Rewriting
To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code verify function for use
in standard serial I/O mode.
ROM code protect function
The ROM code protect function reading out or modifying the contents of the flash memory version by
using the ROM code protect control address (0FFFFFF16) during parallel I/O mode. Figure 30.9 shows
the ROM code protect control address (0FFFFFF16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents
of the flash memory version are protected against readout and modification.
If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM Code Protect Control Address⁽⁵⁾
b7 b6 b5 b4 b3 b2 b1 b0
1111 11
Symbol
ROMCP
Address
FFFFFF16
Factory Setting
FF16(4)
Bit
Symbol
Bit Name
Function
RW
Reserved Bit
Set to "1"
RW
(b5 - b0)
b7 b6
0 0 : ROM code protection active
ROMCP1
ROM Code Protect
Level 1 Set Bit^{(1, 2, 3, 4)}
0 1 : ROM code protection active
1 0 : ROM code protection active
RW
1 1 : ROM code protection inactive
NOTES:
1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected
against reading or rewriting in parallel I/O mode.
2. Set the bit 5 to bit 0 to "1111112" when the ROMCP1 bit is set to a value other than "112".
If the bit 5 to bit 0 are set to values other than "1111112", the ROM code protection may not become
active by setting the ROMCP1 bit to a value other than "112".
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard
serial I/O mode or CPU rewrite mode.
4. The ROMCP address is set to "FF16" when a block, including the ROMCP address, is erased.
5. When a value of the ROMCP address is "0016" or "FF16", the ROM code protect function is disabled.
Figure 30.9 ROM code protect control address
Rev.1.00 Aug. 02, 2005 ^{Page 288} of 329
REJ09B0187-0100