M16C80 Datasheet, PDF (136/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
16. Serial I/O
(UART0)
RxD0
Clock source selection
f1
Internal
f8
f32
Bit rate
generator
1 / (n0+1)
External
UART reception
1/16
Clock synchronous type
Reception
control circuit
UART transmission
1/16
Clock synchronous type
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
CLK0
CTS0 / RTS0
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS selected
CTS0 from UART1
CTS/RTS separated
CTS/RTS disabled
Vss
Clock synchronous type
(when external clock is
selected)
RTS0
CTS0
Receive
clock
Transmit
clock
Transmit/
receive
unit
TxD0
(UART1)
RxD1
Clock source selection
f1
f8
Internal
f32
Bit rate
generator
1 / (n1+1)
External
UART reception
1/16
Clock synchronous type
Reception
control circuit
UART transmission
1/16
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
1/2
Transmission
control circuit
Receive
clock
Transmit
clock
Transmit/
receive
unit
CLK1
CTS1 / RTS1
/ CTS0 / CLKS1
CLK
polarity
reversing
circuit
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
CTS/RTS separated
Clock output pin
select switch
CTS/RTS disabled
RTS1
CTS1
(UART2)
RxD2
RxD polarity
reversing circuit
Clock source selection
f1
Internal
f8
f32
Bit rate
generator
1 / (n2+1)
External
VSS
CTS0
CTS0 to UART0
UART reception
1/16
Clock synchronous type
Reception
control circuit
UART transmission
1/16
Clock synchronous type
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
Receive
clock
Transmit
clock
Transmit/
receive
unit
TxD
polarity
reversing
circuit
CLK2
CTS2 / RTS2
CLK
polarity
reversing
circuit
Clock synchronous type
(when internal clock is selected)
CTS/RTS _{CTS/RTS disabled}
selected
Clock synchronous type
(when external clock is
selected)
RTS2
TxD1
TxD2
CTS/RTS disabled _CTS2
Vss
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Figure 16.1 Block diagram of UARTi (i = 0 to 2)
Rev.1.00 Aug. 02, 2005 ^{Page 125} of 329
REJ09B0187-0100