M16C80 Datasheet, PDF (74/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
ADIC
007316
BCNiIC(i=2 to 4)
008F16, 007116, 009116
DMiIC(i=0 to 3)
006816, 008816, 006A16, 008A16
KUPIC
009316
TAiIC(i=0 to 4)
006C16, 008C16, 006E16, 008E16, 007016
TBiIC(i=0 to 5) 009416, 007616, 009616, 007816, 009816, 006916
SiTIC(i=0 to 4)
009016, 009216, 008916, 008B16, 008D16
SiRIC(i=0 to 4)
007216, 007416, 006B16, 006D16, 006F16
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Bit symbol
Bit name
ILVL0
Interrupt priority level
select bit
ILVL1
ILVL2
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
(Note)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
INTiIC(i=0 to 5) 009E16, 007E16, 009C16, 007C16, 009A16, 007A16 XX00X0002
Bit symbol
Bit name
ILVL0
Interrupt priority level
select bit
ILVL1
ILVL2
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
(Note 2)
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
IR
Interrupt request bit
POL
Polarity select bit
LVS
Level sense/edge
sense select bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge or L level
1 : Selects rising edge or H level
0 : Edge sense
1 : Level sense (Note 3)
(Note 1)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: When INT3 to INT5 are used for data bus in microprocessor mode or memory
expansion mode, set the interrupt disabled to INT3IC, INT4IC and INT5IC.
Note 3: When level sense is selected, set related bit of interrupt cause select register (
address 031F16) to one edge.
Figure 9.3 Interrupt control register
Rev.1.00 Aug. 02, 2005 ^{Page 63} of 329
REJ09B0187-0100