M16C80 Datasheet, PDF (290/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
30. CPU Rewrite Mode
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the BCLK as shown below using the main clock division register (ad-
dress 000C16):
6.25 MHz or less when wait bit (bit 2 at address 000516) = 0 (without internal access wait state)
12.5 MHz or less when wait bit (bit 2 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
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used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can
be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") upon occur-
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rence of the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer inter-
rupts occur, set the CPU rewite mode select bit to "1" and the erase/program operation needs to be
performed over again.
(4) Reset
Reset input is always accepted.
(5) Access disable
Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit
in an area other than the internal flash memory.
(6) How to access
For CPU rewrite mode select bit, lock bit disable bit, and flash memory power supply-OFF bit to be set
to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it
is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed
during the interval.
Write to the CPU rewrite mode select bit when NMI pin is "H" level.
(7)Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,
those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be
rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O
mode to rewrite these blocks.
(8)Using the lock bit
To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.
Rev.1.00 Aug. 02, 2005 ^{Page 279} of 329
REJ09B0187-0100