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M16C/80 Group
18. Clock asynchronous serial I/O (UART) mode
18. Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 18.1 and 18.2 list the specifications of the UART mode. Figure 18.1 shows the
UARTi transmit/receive mode register.
Table 18.1 Specifications of UART Mode (1)
Item
Specification
Transfer data format
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
• When internal clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816,
02F816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816,
02F816 =“1”) : fEXT/16(n+1)(Note 1) (Note 2)
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16,
02FD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16,
032D16, 02FD16) = “0”
_______
_______
- When CTS function selected, CTS input level = “L”
- TxD output is selected by the corresponding function select register A, B
and C.
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16,
02FD16) = “1”
- Start bit detection
Interrupt request
• When transmitting
generation timing
- Transmit interrupt cause select bits (bits 0,1 at address 037016, bit 4 at
address 033D16, 032D16, 02FD16) = “0”: Interrupts requested when data transfer
from UARTi transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 037016, bit 4 at
address 033D16, 032D16, 02FD16) = “1”: Interrupts requested when data
transmission from UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Rev.1.00 Aug. 02, 2005 ^{Page 144} of 329
REJ09B0187-0100