M16C80 Datasheet, PDF (344/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
Revision History
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date
REV.C
Page 58 Table 1.9.3 Software interrupt number 40,41, Add fault error, Add Note 2
Page 59 Interrupt control register Line 4 delate
Page 64 Interrupt sequence (1)
Page 66 Saving registers Last line added
Page 67 Interrupt Priority *1 delated, Last line added
Page 72 (2) Setting the stack pointer Last line added
Page 74 Watchdog timer Line 2
A watchdog timer interrupt is generated when --> Whether a watchdog timer interrupt
is generated or reset is selected when
Last part :Watchdog timer function select bit is initialized only at reset. After reset,
watchdog timer interrupt is selected. added
Page 75 Figure 75 System clock control register 0 added
Page 97 Figure 1.13.9 Count value
Page 181 Figure 1.25.4
Page 182 Figure 1.25.5
Page 131 Figure 1.16.12 Both register Note2 added
Page 135 Table 1.17.3 RxDi bit 1 and 6 at address 03C716 --> bit 1 and 7 ...
Page 132 Table 1.18.3 RxDi bit 1 and 6 at address 03C716 --> bit 1 and 7 ...
Page 147 Figure 1.19.1 Upper figure changed, note added
Page 153 Bit 4 overflow --> underflow
Page 154 Figure 1.20.3 overflow --> underflow
Page 159 Clock phase setting
UARTi transmission-reception control register 0 ..., whereas UARTi special mode
register 3 ... --> Bit 6 of UARTi transmission-reception control register 0 ..., whereas
bit 1 of UARTi special mode register 3 ...
Line 15
... output is high impedance. --> ... output is indeterminate.
Page 171 Line 3 Set the function select register A to I/O port and the direction register to
input mode. added
Page 171 Figure 1.22.2 Note delate
Page 176 Figure 1.24.3 added
Page 178 Figure 1.25.1 When reset --> indeterminate, Note 4 is added.
Page 200 Table 1.26.2 and 1.26.3 and Figure 1.26.14
CNVss is added
Page 204- Electric characteristics added
Rev.C1 Page 214 Table 1.28.22
Page 220 Figure 1.28.6
Page 223 Figure 1.28.9
th(BCLK-DW) add
th(BCLK-CAS) --> th(BCLK-DW)
WR, WRL, WRH(sepalate bus) wave change
Rev.C2 Page 24 Line 3
same ...
A software reset has almost the same ... --> A software reset has the
Page 161 Note 2:
When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. -->
addition
Page 18 Figure 1.4.3
Page 19 Figure 1.4.4
Page 22 Figure 1.5.3
(60) Timer B3,4,5 count start flag value change
Flash memory control register 0 and 1 added
Flash memory control register 0 and 1 added
99.5.12
99.5.20
99.6.4
99.7.6
C-4