M16C80 Datasheet, PDF (81/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
High Priority level of each interrupt
DMA0
Level 0 (initial value)
DMA1
DMA2
DMA3
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
UART0 transmission
UART0 reception
UART1 transmission
UART1 reception
Timer B0
Timer B1
Timer B2
INT1
INT0
Timer B5
UART2 transmission/NACK
UART2 reception/ACK
UART3 transmission/NACK
UART3 reception/ACK
UART4 transmission/NACK
UART4 reception/ACK
Bus collision/start, stop
condition(UART2)
Bus collision/start, stop
condition/fault error (UART3)
Bus collision/start, stop
condition/fault error (UART4)
A/D conversion
Key input interrupt
Timer B3
Timer B4
Stop/wait return interrupt level
(RLVL)
INT5
INT4
INT3
INT2
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
Processor interrupt priority level
(IPL)
Interrupt enable flag (I flag)
Instruction fetch
Address match
Watchdog timer
DBC
NMI
Reset
Figure 9.8 Interrupt resolution circuit
9. Interrupt Outline
Interrupt request priority
detection results output
(to clock generation circuit)
Interrupt
request
accepted.
To CPU
Rev.1.00 Aug. 02, 2005 ^{Page 70} of 329
REJ09B0187-0100