M16C80 Datasheet, PDF (197/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
25. DRAM Controller
The DRAM self-refresh operates in STOP mode, etc.
When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction,
simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert
two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self-
refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.
Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Shifting to self-refresh
•••
mov.b #00000001b,DRAMCONT ;DRAM ignored, one wait is selected
mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait
nop
;Two nops are needed
nop
;
•••
Disable self-refresh
•••
mov.b #00000001b,DRAMCONT
mov.b
nop
nop
•••
#00001011b,DRAMCONT
;Disable self-refresh, DRAM ignored, one wait is
;selected
;Select 4MB and one wait
;Inhibit instruction to access DRAM area
Figures 25.4 to 25.6 show the bus timing during DRAM access.
Rev.1.00 Aug. 02, 2005 ^{Page 186} of 329
REJ09B0187-0100