M16C80 Datasheet, PDF (148/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
17. Clock synchronous serial I/O mode
17. Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 17.1
and 17.2 list the specifications of the clock synchronous serial I/O mode. Figure 17.1 shows the UARTi
transmit/receive mode register.
Table 17.1 Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• When internal clock is selected (bit 3 at addresses 036016, 036816, 033816,
032816, 02F816 = “0”) : fi/ 2(n+1) (Note) fi = f1, f8, f32
_ _{CLK is selected by the corresponding port function select register, periph-}
eral function select register and peripheral subfunction select register.
• When external clock is selected (bit 3 at addresses 036016, 036816, 033816 ,
032816, 02F816= “1”) : Input from CLKi pin
_ _{Set the corresponding function select register A to I/O port}
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_ _{Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “0”}
_______
_______
_ _{When CTS function selected, CTS input level = “L”}
_ _{TxD output selected by the corresponding function select register A, B and C.}
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,}
032C16, 02FC16) = “0”: CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,}
032C16, 02FC16) = “1”: CLKi input level = “L”
Reception start condition
• To start reception, the following requirements must be met:
_ _{Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1”}
_ _{Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “0”}
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,}
032C16, 02FC16) = “0”: CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,}
032C16, 02FC16) = “1”: CLKi input level = “L”
Interrupt request
generation timing
• When transmitting
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at address}
033D16, 032D16, 02FD16) = “0”: Interrupts requested when data transfer from
UARTi transfer buffer register to UARTi transmit register is completed
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at}
address 033D16, 032D16, 02FD16) = “1”: Interrupts requested when data
transmission from UARTi transfer register is completed
• When receiving
_ _{Interrupts requested when data transfer from UARTi receive register to}
UARTi receive buffer register is completed
Note : “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Rev.1.00 Aug. 02, 2005 ^{Page 137} of 329
REJ09B0187-0100