M16C80 Datasheet, PDF (75/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
Exit priority register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RLVL
Address When reset
009F16 XXXX00002
Bit symbol
RLVL0
RLVL1
RLVL2
Bit
Interrupt pⁿri^aor^mity^eset bit for
exiting Stop/Wait state
(Note 1,2)
Function
b2 b1 b0
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
FSIT
High-speed interrupt
set bit (Note 3)
0: Interrupt priority level 7 = normal
interrupt
1: Interrupt priority level 7 = high-speed
interrupt
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is
higher than that set in the exit priority register.
Note 2: Set to the same value as the processor interrupt priority level (IPL) set in
the flag register (FLG).
Note 3: The high-speed interrupt can only be specified for interrupts with
interrupt priority level 7. Specify interrupt priority level 7 for only one
interrupt.
Figure 9.4 Exit priority register
9.7 Interrupt Enable Flag (I Flag)
The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set
(= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag
is automatically cleared to 0 after a reset is cleared.
9.8 Interrupt Request Bit
This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared to 0 by
hardware when the interrupt request is acknowledged and jump to the interrupt vector.
This bit can be cleared to 0 (but cannot be set to 1) in software.
9.9 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When
an interrupt request is generated, the interrupt priority level of this interrupt is compared with the
processor interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is
greater than the processor interrupt priority level (IPL). This means that you can disable any particu-
lar interrupt by setting its interrupt priority level to 0.
Rev.1.00 Aug. 02, 2005 ^{Page 64} of 329
REJ09B0187-0100