M16C80 Datasheet, PDF (154/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
17. Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the port function select register (bits of related to-P64 and P65). (See Figure 17.5) The
multiple pins function is valid only when the internal clock is selected for UART1. Note that when this
_______ _______
function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 17.5 The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 037016, bit 5 at address 033D16,
032D16, 02FD16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the
receive buffer register is read out, the unit simultaneously goes to a receive enable state without
having to set dummy data to the transmit buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2 to UART4)
When the data logic select bit (bit6 at address 033D16, 032D16, 02FD16) = “1”, and writing to transmit
buffer register or reading from receive buffer register, data is reversed. Figure 17.6 shows the ex-
ample of serial data logic switch timing.
•When LSB first
Transfer clock ^{“H”}
“L”
TxDi ^{“H”}
(no reverse) _{“L”}
TxDi ^{“H”}
(reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Figure 17.6 Serial data logic switch timing
Rev.1.00 Aug. 02, 2005 ^{Page 143} of 329
REJ09B0187-0100