M16C80 Datasheet, PDF (162/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)
19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some
extra settings in UART2 to UART4 clock-asynchronous serial I/O mode allows the user to effect this function.
Table 19.1 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
Table 19.1 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
Specification
Transfer data format
• Transfer data 8-bit UART mode (bit 2 to 0 of addresses 033816, 032816, 02F816 = “1012”)
• One stop bit (bit 4 of addresses 033816, 032816, 02F816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and 6 of addresses 033816, 032816, 02F816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 033D16, 032D16, 02FD16 = “0”).
Set transfer format to LSB (bit 7 of address 033C16, 032C16, 02FC16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and 6 of addresses 033816, 032816, 02F816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 033D16, 032D16, 02FD16 = “1”)
Set transfer format to MSB (bit 7 of address 033C16, 032C16, 02FC16 = “1”)
Transfer clock
• With the internal clock chosen (bit 3 of addresses 033816, 032816, 02F816 = “0”)
: fi / 16 (n + 1)
(Note 1) : fi=f1, f8, f32
• With an external clock chosen (bit 3 of addresses 033816, 032816, 02F816 = “1”)
: fEXT / 16 (n+1)
(Note 1) (Note 2)
_______
_______
Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 033C16, 032C16, 02FC16 = “1”)
Other settings
• The sleep mode select function is not available for UART2 and UART3
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 033D16,
032D16, 02FD16 = “1”)
• Set N-channel open drain output to TxD and RxD pins in UART3 and 4 (bit 5 of
address 032C16, 02FC16 = “1”)
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 033D16, 032D16, 02FD16) = “1”
- Transmit buffer empty flag (bit 1 of address 033D16, 032D16, 02FD16) = “0”
Reception start condition • To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 033D16, 032D16, 02FD16) = “1”
- Detection of a start bit
Interrupt request
generation timing
• When transmitting
When data transmission from the UART2 to UART4 transfer register is completed (bit
4 of address 033D16, 032D16, 02FD16 = “1”)
• When receiving
When data transfer from the UART2 to UART4 receive register to the UART2 to
UART4 receive buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TxDi pin by use of the parity
error signal output function (bit 7 of address 033D16, 032D16, 02FD16 = “1”) when a
parity error is detected
- On the transmission side, a parity error is detected by the level of input to the RxDi
pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi
receive interrupt request bit will not change.
Rev.1.00 Aug. 02, 2005 ^{Page 151} of 329
REJ09B0187-0100