M16C80 Datasheet, PDF (76/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
Table 9.4 shows how interrupt priority levels are set. Table 9.5 shows interrupt enable levels in
relation to the processor interrupt priority level (IPL).
The following lists the conditions under which an interrupt request is acknowledged:
• Interrupt enable flag (I flag)
=1
• Interrupt request bit
=1
• Interrupt priority level
> Processor interrupt priority level (IPL)
The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the proces-
sor interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit.
Table 9.4 Interrupt Priority Levels
Interrupt priority
Interrupt priority level
level select bit
Priority
order
b2
0
b1
0
b0
0
Level 0 (interrupt disabled)
0 0 1 Level 1
Low
0 1 0 _{Level 2}
0 1 1 _{Level 3}
1 0 0 Level 4
1 0 1 Level 5
1 1 0 Level 6
1 1 1 _{Level 7}
High
Table 9.5 IPL and Interrupt Enable Levels
Processor interrupt Enabled interrupt priority
priority level (IPL)
levels
IPL2 IPL1 IPL0
000
001
Interrupt levels 1 and above are enabled.
Interrupt levels 2 and above are enabled.
010
011
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
1 0 0 ^{Interrupt levels 5 and above are enabled.}
1 0 1 Interrupt levels 6 and above are enabled.
1 1 0 Interrupt levels 7 and above are enabled.
1 1 1 All maskable interrupts are disabled.
9.10 Rewrite the interrupt control register
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
Rev.1.00 Aug. 02, 2005 ^{Page 65} of 329
REJ09B0187-0100