M16C80 Datasheet, PDF (85/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
9.22 Precautions for Interrupts
(1) Reading addresses 00000016 and 00000216
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence from address 00000016. When high-speed interrupt
is occurred, CPU read from address 00000216.
The interrupt request bit of the certain interrupt will then be set to “0”.
However, reading addresses 00000016 and 00000216 by software does not set request bit to “0”.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 00000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
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the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
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at the beginning of a program. Any interrupt including the NMI interrupt is generated immediately after
executing the first instruction after reset. Set an even address to the stack pointer so that the operating
efficiency of accessign memory is increased.
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(3) The NMI interrupt
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• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistance
(pull-up) if unused. Be sure to work on it.
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• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
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when the NMI interrupt is input.
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• Signals input to the NMI pin require "L" level and "H" level of 2 clock + 300ns or more, from the
operation clock of CPU.
(4) External interrupt
• Edge sense
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
to INT5 regardless of the CPU operation clock.
• Level sense
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division
mode, at least 250 ns width is necessary.)
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 9.12 shows the procedure for
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changing the INT interrupt generate factor.
Rev.1.00 Aug. 02, 2005 ^{Page 74} of 329
REJ09B0187-0100