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M16C80 Datasheet, PDF (167/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES
M16C/80 Group
20. UARTi Special Mode Register (i = 2 to 4)
UARTi special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiSMR (i=2 to 4)
Address
033716, 032716, 02F716
When reset
0016
Bit
symbol
IICM
Bit
name
I2C mode select bit
Function
(During clock synchronous
serial I/O mode)
0 : Normal mode
1 : I2C mode
Function
(During UART mode)
Set to “0”
RW
ABC
BBS
LSYN
Arbitration lost detecting
flag control bit
Bus busy flag
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
Set to “0”
Set to “0”
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Set to “0”
(Note 1)
ABSCS Bus collision detect
Set to “0”
sampling clock select bit
ACSE
SSS
Auto clear function
select bit of transmit
enable bit
Transmit start condition
select bit
Set to “0”
Set to “0”
0 : Rising edge of transfer
clock
(Note 2)
1 : Underflow signal of timer Ai
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
0 : Ordinary
1 : Falling edge of RxDi
Nothing is assigned.
When write, set "0". When read, the content is "0".
Note 1: Nothing but "0" may be written.
Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4
underflow signal.
UARTi special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiSMR2 (i=2 to 4)
Address
033616, 032616, 02F616
When reset
0016
Bit
symbol
Bit name
IICM2 IIC mode select bit 2
CSC Clock synchronous bit
SWC SCL wait output bit
ALS SDA output stop flag
STC UARTi initialize bit
SWC2 SCL wait output bit 2
SDHI SDA output inhibit bit
SHTC Start/stop condition
control bit
Function
Refer to Table 20.2
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : UARTi clock
1 : 0 output
0 : Enabled
1 : Disabled (high impedance)
Set to "1" in selecting IIC mode.
RW
Figure 20.1 UART2 special mode register
Rev.1.00 Aug. 02, 2005 Page 156 of 329
REJ09B0187-0100