M16C80 Datasheet, PDF (98/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
11. DMAC
(1) •When 8-bit data is transferred
•When 16-bit data is transferred on a 16-bit data bus and the source address is even
BCLK
Address
bus
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
CPU use
(2) •When 16-bit data is transferred and the source address is odd
•When 16-bit data is transferred and the width of data bus at the source is 8-bit
(When the width of data bus at the destination is 8-bit, there are also two destination write cycles).
BCLK
Address
bus
CPU use
Source Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
CPU use
Source Source + 1
Destination
CPU use
(3) •When one wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
CPU use
(4) •When one wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred and the width of data but at the destination is 8-bit, there are
two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.6 Example of the transfer cycles for a source read
Rev.1.00 Aug. 02, 2005 ^{Page 87} of 329
REJ09B0187-0100