M16C80 Datasheet, PDF (89/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
10. Watchdog Timer
10. Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer
interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. Watchdog timer
interrupt is selected when bit 6 of the system control register 0 (address 000816 :CM06) is "0" and reset is
selected when CM06 is "1". No value other than "1" can be written in CM06. Once when reset is selected
(CM06="1"), watchdog timer interrupt cannot be selected by software.
When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the
prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for
division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Therefore, the
watchdog timer cycle can be calculated as follows. However, errors can arise in the watchdog timer cycle
due to the prescaler.
When XIN is selected in BCLK
Watchdog timer cycle =
When XCIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
BCLK
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
For example, when BCLK is 20MHz and the prescaler division ratio is set to 16, the monitor timer cycle is
approximately 26.2 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). CM06 is initialized only at reset. After reset,
watchdog timer interrupt is selected.
The watchdog timer and the prescaler stop in stop mode, wait mode and hold status. After exiting these
modes and status, counting starts from the value remained before.
In the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released. Figure 10.1 shows the block diagram
of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers.
BCLK
HOLD
Write to the watchdog timer
start register
(address 000E16)
RESET
Prescaler
1/16
“CM07 = 0”
“WDC7 = 0”
1/128
“CM07 = 0”
“WDC7 = 1”
“CM07 = 1”
1/2
Watchdog timer
Set to
“7FFF16”
"CM06=0"
Watchdog timer
interrupt request
"CM06=1"
Reset
Figure 10.1 Block diagram of watchdog timer
Rev.1.00 Aug. 02, 2005 ^{Page 78} of 329
REJ09B0187-0100