M16C80 Datasheet, PDF (350/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
Revision History
Version
Contents for change
Revision
date
ing) --> "Note 2 Timer A2 is fixed to ... multiply-by-4 processing operation." is added,
note 3 change
Page 109 Figure 1.14.6 Note 1 It is indeterminate when reset --> addition
Page 112 Figure 1.15.2 Dead time timer-->Note 1 addition, Timer B2 interrupt occurrence
frequency set counter-->Note 3 addition
Page 113 Notes 2, 3 --> addition
Page 114 three-phase waveform mode --> three phase PWM output mode
Page 128 Figure 1.16.5 UARTi bit rate generator --> Note 2 addition
Page 128 Figure 1.16.5 UARTi transmit buffer register, UARTi bit rate generator-->Note 1
addition
Page 129 Figure 1.16.6 UARTi transmit/receive mode register-->Note 2 addition in CKDIR of
UART mode
Page 133 Figure 1.16.10 UART transmit/receive control register 2-->Note delete
Page 136 Note 2, Page 143 Note 3 ... the UARTi receive interrupt request bit is not set to "1"
--> ... the UARTi receive interrupt request bit will not change
Page 145 Figure 1.18.1 UARTi transmit/receive mode register (i=0,1) --> Note 1 addition,
UARTi transmit/receive mode register (i=2 to 4) --> Note 2 addition
Page 157 On the 12th line, ... allocated to bit 3 in UART2 transmission buffer register 1
(address 033F16) ... --> ... allocated to bit 11 in UART2 transmission buffer register
(address 033E16) ...
Page 161 < Master Mode (TxDi and RxDi are selected, DINC = 0) >
..., and the STxDi, SRxDi and CLKi pins ...--> ..., and the TxDi, RxDi and CLKi
pins ...
Page 165 Table 1.21.1 Absolute precision --> change
Page 170 Table 1.21.3 Reading of result of A/D converter --> (at any time) addition
Page 173 Table 1.21.6 Input pin --> change to AN0 to AN7, With emphasis on the pin -->
addition
Page 182 On the second line from the bottom, ..., and dummy cycle for refresh ... --> ..., and
processing necessary for dummy cycle to refresh DRAM ...
Page 183 Figure 1.25.2 is partly revised.
Page 189 On the 18th and 27th lines, page 194 Port Pi direction register Note 2, page 196
Port Pi register Note 1 ... for setting of bus control such as address bus and data bus is
_____
_______
_______ _______ _____ _________
... --> of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL,
_______ _______ _______ _____ _____
_________
_________
_______
WRH/BHE/CASH, RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and
_______
RDY are ...
Page 203 Figure 1.26.13 is partly revised.
Page 207, 208 Timer A (event counter mode) --> (3) addition, Timer A (one-shot timer mode)
--> (2) changes to (3), (2) and (4) addition
Page 209 Timer B (pulse period/pulse width measurement mode) --> (3) addition
________
________
Page 212 to 214 (2) NMI interrupt •The NMI pin also serves as P85, ... •Signal of "L" level ...
--> addition
(3) Address match interrupt From "• To return from an interrupt..." to
"; Interrupt completed" on page 77 --> addition
(4) External interrupt, (5) Rewrite the interrupt control register --> addition
Page 215 Explanation of (3) is partly revised.
__________
Page 215 HOLD signal --> addition
Page 216 DRAM controller --> addition
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