M16C80 Datasheet, PDF (59/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
8. Clock Generating Circuit
Table 8.2 Clock output setting (single chip mode)
BCLK output function Clock output function select
select bit
bit
ALE pin select bit
PM07
CM01
CM00
PM15
PM14
0/1
0
0
Ignored Ignored
1
0
1
Ignored Ignored
1
1
0
Ignored Ignored
1
1
1
Note :Must use P57 as input port.
Ignored Ignored
P53/BCLK/ALE/CLKOUT
pin function
P53 I/O port
fc output (Note)
f8 output (Note)
f32 output (Note)
Table 8.3 Clock output setting (memory expansion/microprocessor mode)
BCLK output function Clock output function select
select bit
bit
PM07
CM01
CM00
ALE pin select bit
PM15
PM14
P53/BCLK/ALE/CLKOUT
pin function
0
0
0
BCLK output
1
0
0
0
0
"L" output (not P53)
1
0
1
1
0
fc output
1
1
0
1
1
f8 output
1
1
1
f32 output
Ignored
0
0
0
1
ALE output
8.4 Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation of BCLK, f1 to f32, f1SIO2 to f32SIO2, fc, fc32, and fAD stops in stop mode, peripheral
functions such as the A/D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 8.4 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt.
When using an interrupt to exit stop mode, the relevant interrupt must have been enabled and set to a
priority level above the level set by the interrupt priority set bits (bits 2, 1, and 0 at address 009F16) for
exiting a stop/wait state. Set the interrupt priority set bits for the exit from a stop/wait state to the same level
as the flag register (FLG) processor interrupt level (IPL). Figure 8.6 shows the exit priority register.
The priority level of the interrupt which is not used to cancel stop mode, must have been changed to 0.
When exiting stop mode using an interrupt, the relevant interrupt routine is executed.
______
If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all
interrupt to 0, then shift to stop mode.
When shifting to stop mode and reset, the main clock division register (000C16) is set to “0816”.
Rev.1.00 Aug. 02, 2005 ^{Page 48} of 329
REJ09B0187-0100