M16C80 Datasheet, PDF (49/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
7. Bus
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________
__________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 7.8 shows
the microcomputer status in the hold state. The bus is used in the following descending order of priority:
__________
HOLD, DMAC, CPU.
__________
HOLD > DMAC > CPU
_____
________
Figure 7.5 Example of RD signal extended by RDY signal
Table 7.8 Microcomputer status in hold state
Item
Status
Oscillation
_____ _____
_____ _______
RD/WR signal, address bus, data bus, CS, BHE
ON
Floating
Programmable I/O ports P0, P1, P2, P3, P4, P5
Maintains status when hold signal is received
P6, P7, P8, P9, P10
__________
HLDA
P11, P12, P13, P14, P15 (Note)
Output “L”
Internal peripheral circuits
ON (but watchdog timer stops)
ALE signal
Undefined
Note: Ports P11 to P15 exist in 144-pin version.
(7) External bus status when accessing to internal area
Table 7.9 shows external bus status when accessing to internal area
Table 7.9 External bus status when accessing to internal area
Item
Address bus
SFR accessing status
Internal ROM/RAM accessing status
Remain address of external area accessed immediately before
Data bus When read Floating
When write
_____ ______ ________ _________
RD, WR, WRL, WRH
________
BHE
____
CS
Floating
Output "H"
Remain external area status accessed immediately before
Output "H"
ALE
ALE output
(8) BCLK output
BCLK output can be selected by bit 7 of the processor mode register 0 (address 000416 :PM07) and bit 1
and bit 0 of the system clock select register 0 (address 000616 :CM01, CM00). Setting PM07 to “0” and
CM01 and CM00 to “00” outputs the BCLK signal from P53. However, in single chip mode, BCLK signal
is not output. When setting PM07 to “1”, the function is as set by CM01 and CM00.
Rev.1.00 Aug. 02, 2005 ^{Page 38} of 329
REJ09B0187-0100