M16C80 Datasheet, PDF (60/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
8. Clock Generating Circuit
Table 8.4 Port status during stop mode
Pin
Memory expansion mode
Single-chip mode
_______ _______ _______
Address bus, data bus, CS0 to CS3, BHE
_____ ______ ________ _________ ______ _________
RD, WR, WRL, WRH, DW, CASL,
________
CASH
________
RAS
__________
HLDA, BCLK
Microprocessor mode
Retains status before stop mode
“H” (Note)
“H” (Note)
“H”
ALE
“H”
Port
Retains status before stop mode Retains status before stop mode
CLKOUT When fc selected
“H”
“H”
When f8, f32 selected
Retains status before stop mode Retains status before stop mode
________
________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.
Exit priority register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RLVL
Address When reset
009F16 XXXX00002
Bit symbol
RLVL0
RLVL1
RLVL2
Bit
Interrupt pⁿri^aor^mity^eset bit for
exiting Stop/Wait state
(Note 1,2)
Function
b2 b1 b0
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
FSIT
High-speed interrupt
set bit (Note 3)
0: Interrupt priority level 7 = normal
interrupt
1: Interrupt priority level 7 = high-speed
interrupt
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is
higher than that set in the exit priority register.
Note 2: Set to the same value as the processor interrupt priority level (IPL) set in
the flag register (FLG).
Note 3: The high-speed interrupt can only be specified for interrupts with
interrupt priority level 7. Specify interrupt priority level 7 for only one
interrupt.
Figure 8.6 Exit priority register
Rev.1.00 Aug. 02, 2005 ^{Page 49} of 329
REJ09B0187-0100